Semiconductor chips generally comprise arrays of microelectronic devices, such as transistors, having contacts interconnected by patterns of conductive lines or wires. As the devices on these semiconductor chips become more and more densely packed, for example as is found in the Very Large Scale Integrated (VLSI) circuit technology used today, the interconnect patterns become correspondingly complex. As a result of this complexity, multiple levels of interconnect patterns/wires are required to wire up the many densely packed devices.
Such multiple levels of interconnect wiring, of which two to six are not uncommon for a state-of-the-art VLSI circuit, typically comprise layers of conductive lines separated by intermediary layers of insulating material. These separate levels of conductive lines are electrically interconnected by conductive studs extending through vias in the insulating layers.
As the complexity of the interconnect levels increases in correspondence with the density of the devices on the semiconductor chips, problems are encountered in forming the conductive lines and studs to the necessarily more stringent tolerances. Typical prior art processes, for example, require the use of multiple masks and lift-off steps to form the conductive lines and studs. In addition to the alignment problems and errors inherent in the use of multiple masking steps, these processes are complex, lengthy, and often require the use of several expensive, specialized manufacturing tools.
U.S. Pat. No. 4,721,689 to Chaloux, Jr. et al., assigned to the assignee of the present invention, shows a method for simultaneously forming an interconnection level over, and via studs through, an insulating layer of a semiconductor chip. The method comprises the steps of forming a plurality of via holes in the insulating layer, high-mobility sputtering conductive material onto the surface of the insulating layer and into the via holes, masking the conductive material layer, and ion beam milling through the mask to form a patterned interconnection layer.
The Chaloux, Jr. et al. patent suffers from the disadvantage of requiring two separate masking steps: the first to define the via holes and the second to define the patterned interconnection layer. The resulting product suffers from the alignment errors inherent in the use of the two masking steps. The patent further requires the etching of two highly disparate materials: the insulator defining the via holes, and the metal. This likely requires the use of two separate processing tools.
U.S. Pat. No. 4,541,893 to Knight shows a process for fabricating pedestal interconnections between conductive layers in an integrated circuit, including the steps of: (a) forming a first conductive layer over a semiconductor substrate; (b) applying a stop etch layer to the first conductive layer, the stop etch layer having a different etch property than the first conductive layer; (c) patterning the first conductive layer and the stop etch layer in an interconnection pattern which includes widened regions wherever a pedestal interconnection is to be formed; (d) selectively etching the stop etch layer until the stop etch layer remains as a stop etch cap only in central sections of the widened region; and (e) selectively etching the first conductive layer to a selected depth whereby a pedestal is formed underneath the stop etch caps.
Knight suffers from the disadvantage of requiring the widened regions (step (c)) to accommodate process tolerances and misalignments where pedestals are to be formed. These widened areas waste semiconductor chip space by limiting the minimum inter-wire distances. Further, too severe a misalignment in the forming of a widened region may result in the formation of an insufficiently small stud, or in no stud at all.
The following references each show the use of a dual tone photoresist in a self-aligning lithographic process. None of the references show or suggest the use of such a photoresist or process to form self-aligned conductive studs on lines.
U.S. Pat No. 4,767,723 to Hinsberg, III et al., assigned to the assignee of the present invention, shows a process for making thin film transistors using a dual tone photoresist.
Published European Patent Application 0 220 578 to Hinsberg, assigned to the assignee of the present invention, shows several embodiments of a dual tone photoresist. The application further shows the use of such a dual tone photoresist to form self-aligned structures on an underlying substrate.
The article, "Zero-Misalignment Lithographic Process Using A Photoresist with Wavelength-Selected Tone", to Hinsberg et al., SPIE Vol. 920, Advances in Resist Technology and Processing V, 1988, shows a dual tone photoresist, a mask for use with such a photoresist, and a self-aligning lithographic process utilizing the photoresist and mask.